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STA001
RF FRONT-END FOR DIGITAL RADIO
PRODUCT PREVIEW
s s s s s s s s s s s s
SINGLE CHIP RECEIVER FOR SATELLITE DIGITAL TRANSMISSION SUPERHETERODYNE RECEIVER WITH IF OUTPUT HIGH INPUT INTERCEPT POINT, LOW MIXER NOISE 54dB IF VGA GAIN RANGE ADJUSTABLE RF GAIN ADJUSTABLE IF GAIN INTEGRATED RF VCO INTEGRATED IF VCO INTEGRATED SYNTHESIZER I2CBUS COMPATIBLE PROGRAMMING INTERFACE UNREGULATED 2.7 V TO 3.3V VOLTAGE SUPPLY LOW COST EXTERNAL COMPONENTS
TQFP44 ORDERING NUMBER: STA001
HSB2 High Speed Bipolar Technology for one chip solution for the Starman digital satellite radio receiver. The STA001 is assembled in a TQFP44 package. The frontend architecture is a double conversion receiver (see block diagram) . The chip includes all the RF functions up to low IF and manages the signals to and from the baseband.
DESCRIPTION The STA001 is an RF IC using STMicroelectronics BLOCK DIAGRAM
AGC1, AGC2 PADJ1, PADJ2 VDD1 SUPPLY1 :RF VSS1 LNI, NLNI LNA IF1 BUFFER VGA 1338.14 - 1375.4 MHz FLT1 113.23KHz TK1, NTK1
CHARGE PUMP CHARGE PUMP
CE
SIP, SIN
SOP, SON GADJ1, GADJ2 SUPPLY4 :IF1, IF2 &PLL2 IF1 to IF2 MIXER IF2 BUFFER RXI, NRXI 1.8366 Mhz FLT2 TK2, NTK2 VDD4 VSS4
RF MIXER
117.0806 MHz
1st PLL 3.68MHz
VCO PHASE DETECTOR
PHASE DETECTOR
VCO
: 1034
DIFFERENTIAL SINGLE ENDED
ENRFOSC
LOCK DETECTOR
:130 :4
:363.625- 373.75
2nd PLL
TLCK
14.72MHz
BUFFER
M_CLK VDD3
VDD2 VSS2
SUPPLY2 :PLL1 + Crystal osc .
MUX I2CBUS INTERFACE
OSC
SUPPLY3 :DIG. VSS3
CHANNEL SELECTION SDA SCL XOSEL REF
XTAL1, XTAL2
November 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
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STA001
PIN CONNECTION (Top view)
AGC1 AGC2 VDD4 VDD4
35
VSS4
VSS4
NTK2
44
43
42
41
40
39
38
37
36
FLT2
34 33 32 31 30 29 28 27 26 25 24 23
SON
SOP
TK2
VDD1 SIP SIN VSS1 LNI NLNI VSS1 N.C. PADJ1 PADJ2 ENRFOSC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
RXI NRXI GADJ1 GADJ2 CE VDD3 SCL SDA VSS3 M_CLK1 M_CLK2
VDD2
TK1
NTK1
VDD2
FLT1
VSS2
XTAL1
XTAL2
REF
XOSEL
TLCK
D97AU602
PIN FUNCTION
N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Pin VDD1 SIP SIN VSS1 LNI NLNI VSS1 NC PADJ1 PADJ2 Positive supply 1 SAW filter input connection SAW filter input connection Negative supply 1 RF input RF input Negative supply 1 Not connected RF gain adjust connection 1 RF gain adjust connection 2 Function
ENRFOSC RF Oscillator enable VDD2 TK1 NTK1 VDD2 FLT1 VSS2 XTAL1 XTAL2 REF XOSEL TLCK Positive supply 2 1st PLL tank connection 1 1st PLL tank connection 2 Positive supply 2 1st PLL loop filter connection Negative supply 2 Quartz oscillator connection 1 Quartz oscillator connection 2 External optional TCXO input Internal/external XO selection Lock detector output
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STA001
PIN FUNCTION (continued)
N 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin M_CLK2 M_CLK1 VSS3 SDA SCL VDD3 CE GADJ2 GADJ1 NRXI RXI FLT2 VDD4 TK2 NTK2 VDD4 AGC2 AGC1 VSS4 SON SOP VSS4 Master clock differential output 1 Master clock differential output 2 Negative supply 3 Data serial input Clock input Positive supply 3 Chip Enable IF gain adjust connection 2 IF gain adjust connection 1 Low IF Signal output 2 Low IF Signal output 1 2nd PLL loop filter connection Positive supply 4 2nd PLL tank connection 2nd PLL tank connection Positive supply 4 VGA control pin 2 VGA control pin 1 Negative supply 4 SAW filter output connection SAW filter output connection Negative supply 4 Function
ABSOLUTE MAXIMUM RATINGS
Symbol Tstg Toper Vmax Vmin Vmaxi VDDmax Vesd Storage temperature Operative ambient temperature Maximum voltage on any pin (with the exception of CE, SDA, SDL) Minimum voltage on any pin Maximum voltage on pins CE, SDA, SDL Minimum/Maximum power supply between VDD1,2,3,4 and VSS1,2,3,4 Electrostatic Discharge Voltage (ESD) Parameter Value -40 , +125 -20 , +85 VDD+0.3 GND-0.3 VDD+0.6 -0.3/5.5 2 Unit C C V V V V KV
OPERATING CONDITIONS
Symbol VDD Tjun Operating voltage Junction temperature Parameter Value 2.7, 3.3 -30, +95 Unit V C
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STA001
THERMAL DATA
Symbol Parameter Value 45 Unit C/W
RTh j-amb Thermal Resistance Junction to Ambient (1)
(1) According to JEDEC specification on a 4 layers board
ELECTRICAL CHARACTERISTCS
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY CURRENTS (Tamb = 25, VDD = 3V) ICC1 ICC2 Current supplied by VDD1 Current supplied by VDD2 Powered circuits: LNA, RF mixer, IF buffer Powered circuits: RF pll, Crystal Oscillator. ENRFOSC=high (IC RF Osc. Enabled), XOSEL=high (IC XO Enabled) ENRFOSC=low (IC RF Osc. Disabled), XOSEL=high (IC XO Enabled) ENRFOSC=high (IC RF Osc. Enabled), XOSEL=low (IC XO Disabled) ENRFOSC=low (IC RF Osc. Disabled), XOSEL=low (IC XO Disabled) ICC3 ICC4 Current supplied by VDD3 Current supplied by VDD4 ICC1+ ICC2+ ICC3+ ICC4 Powered circuits: Digital cells Powered circuits: VGA, IF mixer, output buffer, IF pll. V(AGC1)=V(AGC2)=1.2 (IFgain=75dB) ENRFOSC=high (IC RF Osc. Enabled), XOSEL=high (IC XO Enabled) ENRFOSC=low (IC RF Osc. Disabled), XOSEL=high (IC XO Enabled) ENRFOSC=high (IC RF Osc. Enabled), XOSEL=low (IC XO Disabled) ENRFOSC=low (IC RF Osc. Disabled), XOSEL=low (IC XO Disabled) ITOTSB Standby ICC1+ ICC2+ ICC3+ ICC4 CE=GND 9.5 14 17 mA
8.5
10
12
mA
3
5
6
mA
7.5
9
11
mA
2 12 7
4 15 11
5 18 14
mA mA mA
ITOT
40
50
61
mA
34
45
55
mA
39
49
60
mA
34
44
54 100
mA A
LNA, RF MIXER AND IF1 BUFFER (T = 25, VDD-VSS = 3V) BWi BWo GV Input signal BW Output signal BW Voltage Gain Input LNI, NLNI pins; output SIP, NIP pins. RL = 200, PADJ1, PADJ2 floating 1452 114 28 30 1492 116.5 33 MHz MHz dB
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STA001
ELECTRICAL CHARACTERISTCS (continued)
Symbol GVtrim Zi Zo Rl IIP3 IIP3trim 1dBcp 1dBcptri
m
Parameter Minimum Voltage Gain Input impedance R || C Output impedance Input Return Loss Input IP3 Input IP3 minimum gain Input 1 dB compression point Input 1 dB compression point Noise figure contribution
Test Condition Input LNI, NLNI pins; output SIP, NIP pins. RL = 200, Rext=0 Balanced, LNI, NLNI pins Balanced, SIP, SIN pins LNI, NLNI pins Input LNI, NLNI pins; output SIP, NIP pins, Rl=200, PADJ1, PADJ2 floating Input LNI, NLNI pins; output SIP, NIP pins, Rl=200, Rext=0 on PADJ1, PADJ2 Input LNI, NLNI pins; output SIP, NIP pins, Rl=200, PADJ1, PADJ2 floating Input LNI, NLNI pins; output SIP, NIP pins, Rl=200, PADJ1, PADJ2 Rext=0 on PADJ1, PADJ2 Measurement conditions: Input LNI, NLNI pins; output SIP, NIP pins. Rs=50, Rl=200, DSB, PADJ1, PADJ2 floating Measurement conditions: Input LNI, NLNI pins; output SIP, NIP pins. Rs=50, Rl=200, DSB, Rext=0 on PADJ1, PADJ2
Min. 22
Typ. 25 75 0.2 50 14
Max. 28
Unit dB pF dB
-20 -19.5 -26 -24
-15 -11.5
dBm dBm dBm dBm
NF
5
dB
NFtrim
Noise figure contribution minimum gain
6.5
dB
IF1leak RFleak VDC VDC
LO1 to IF1 leakage LO1 to RF leakage LNI, NLNI common mode AC coupled to the Balun DC voltage SIP, SIN common mode DC voltage AC coupled to the SAW filter
-100 -100 VDD1.2 VDD1.3 VDD-1 VDD1.1
-25 -30 VDD0.8 VDD0.9
dBm dBm V V
IF VGA AMPLIFIER, IF MIXER AND OUTPUT BUFFER (T = 25, VDD-VSS = 3V) BWi BWo Gmin Gmax IAGC ZAGC Input signal BW Output signal BW Minimum gain Maximum gain Input current in AGC control pin AGC pin input impedance Input LNI, NLNI pins; output SIP, NIP pins. Rl=high impedance V(AGC1,2)=0V Input LNI, NLNI pins; output SIP, NIP pins. Rl=high impedance V(AGC1,2)=3V 71 114 0.6 32 86 10 600 116.5 3.1 37 MHz MHz dB dB A K
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STA001
ELECTRICAL CHARACTERISTCS (continued)
Symbol NF Parameter Noise figure contribution Test Condition Measurement conditions: Input SIP, NIP pins; output SOP, NOP pins. Rs=50, Rl=200, DSB, Gain = 65dB Gain = 65dB Gain = 81dB Gain = 65dB Gain = 81dB Balanced, SOP, SON pins Balanced, RXI, NRXI pins (see fig. 9) AC coupled to the SAW filter VDD1.2 VDD2.1 VDD0.15 Balanced, GADJ1, GADJ2 pins Obtained using low pass filter at the output Obtained with SAW filter connected to IF port Vout=1VDDp -100 -30 VDD0.12 800 -45 -30 Min. Typ. 9 Max. Unit dB
1dBcp 1dBcpfg IIP3 IIP3fg Zin Zout VDC VDC VDC Zadj BBleak IF2leak IM3
Input 1 dB compression point Input 1 dB compression point full gain Input IP3 Input IP3 full gain Input impedance Output impedance SOP, SON common mode DC voltage RXI, NRXI common mode DC voltage GADJ1, GADJ2 common mode DC voltage Gain adjustment pins impedance LO2 to BB leakage LO2 to IF2 leakage Third order IM product
-50 -66 -41 -57 50 200 VDD-1 VDD0.8 VDD1.36 VDD
dBm dBm dBm dBm V V V dBm dBm dBc
Figure 1. Typical IF Overall Gain vs Control Voltage
IF TOTAL VOLTAGE GAIN (dB)
input SOP,NOP output RXI,NRXI
IF TOTAL VOLTAGE GAIN (dB)
input SOP,NOP output RXI,NRXI
60
90
IF TOTAL VOLTAGE GAIN (dB)
55
IF TOTAL VOLTAGE GAIN (dB)
85
50
IF gain (dB)
80
IF gain (dB)
45
75
40
70
65
35
60
30 0.7 0.75 0.77 0.79 0.8 0.82 0.84 0.86 0.88 0.9
1 1.1
1.2 1.3
1.4 1.5
1.6 1.7
1.8 1.9
2 2.1
2.2 2.3
2.4 2.5
2.6 2.7
V(AGC1, AGC2) (Volt)
V(AGC1, AGC2) (Volt)
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STA001
ELECTRICAL CHARACTERISTCS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
CRYSTAL OSCILLATOR (T = 25, VDD-VSS = 3V) VDC XTAL1, XTAL2 common mode DC voltage XOSEL high VDD1.1 VDD0.68 V
PLLs, SYNTHESIZERS (T = 25, VDD-VSS = 3V) ts Pn fREF1 fREF2 PSP Nprog1 RF pll loop settling time Total phase noise contribution RF pll comparation frequency IF pll comparation frequency Spurious power level*** RF pll, fc=n*460KHz n=1,2.. IF pll, fc=113.23KHz from REF1 to LO1, range covered by a 0.5 step, using a 14.72MHz quartz -100 1443 (first used 1454.5) 1443 (first used 1454) 987 1034 4 130 within 1 KHz final freq. Offset, by using the loop filter of Application board 100Hz < f < 1.84Mhz, Qrf_tank20, Qif_tank20 1 1.6 3.68 113.23 -50 -45 1506.5 (last used 1495) 1506.5 (last used 1494.5) 1081 ms degrms MHz KHz dBc dBc
RF PLL selectable division ratios
Nprog2
RF PLL selectable division ratios
from REF1 to LO1, range covered by a 0.5 step, using a 14.725MHz quartz
Nfix NREF1 NREF2
IF PLL fixed division ratios from REF2 to LO2, 1 fixed +2 testing values REF1 division ratio REF2 division ratio from Crystal oscillator to REF1 from Crystal oscillator to REF2
*** Using loop filter as suggested in application board schematics
RF VCO (T = 25, VDD-VSS = 3V) fLO1_1 fLO1_2 VFLT1 VDC Zi LO Freq. range LO Freq. range Freq. control voltage range TK1, NTK1 DC voltage Input impedance R || C Using 14.72Mhz quartz Using 14.725Mhz quartz Pin FLT1 ENRFOSC high Balanced, TK1, NTK1 pins 1338.14 1375.4 MHz MHz V V pF
1338.134375 to 1375.407031 VSS + 0.2 VDD1.3 VDD1.1 300 0.2 VDD 0.2 VDD0.65
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STA001
ELECTRICAL CHARACTERISTCS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
IF VCO (T = 25, VDD-VSS = 3V) fLO2_1 LO Freq. Using a 14.72MHz quartz, Min. and Max. Values are optional fixed frequency usable for testing purposes. Using a 14.725MHz quartz, Min. and Max. Values are optional fixed frequency usable for testing purposes. FLT2 pin 111.76 117.08 122.4 MHz
fLO2_2
LO Freq.
111.8
117.12
122.44
MHz
VFLT2
Freq. control voltage range
VSS + 0.2
VDD 0.2
V
DIGITAL INTERFACE TO MP (SCL, SDA, TLCK) AND XOSEL INTERFACE (T = 25, VDD-VSS = 3V) INPUT PARAMETERS (SCL, SDA) VIH VIL IIH IIL Tt Rin Input current High Input current Low Input edge transition Input resistance digital input signals high low VDD-1 VSS 10 -40 0.1 190K VDD VSS+0. 7 V V A A s/V
OUTPUT PARAMETERS (TLCK) VOH VOL tr tf Rise time Fall time digital output signals high low Cl=5pF Cl=5pF VDD0.5 VSS 0.4 0.4 VDD VSS+0. 5 V V s/V s/V
DIFFERENTIAL DIGITAL INTERFACE (M_CLK1, M_CLK2) (T = 25, VDD-VSS = 3V) VOH VOL VDC tr tf Zout digital output signals, V(M_CLK1) V(M_CLK2) M_CLK1, M_CLK2 common mode DC voltage Rise time Fall time Output impedance Cl=5pF each pin Cl=5pF each pin balanced high low VDD1.12 10 10 500 0.2 -0.2 VDD0.7 V V V ns ns
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STA001
ELECTRICAL CHARACTERISTCS (continued)
Symbol fM_CLK1 fM_CLK2 Parameter M_CLK frequency M_CLK frequency Test Condition Using a 14.72MHz quartz Using a 14.725MHz quartz Min. Typ. 14.72 14.725 Max. Unit MHz MHz
ADDITIONAL DIGITAL INTERFACE (CE) (T = 25, VDD-VSS = 3V) (LOW=GND, HIGH=VDD) VIH VIL tr tf CE power up time CE power down time digital input signals high low 2 6 VSS+1. 8 VSS+1. 3 V V s s
XOSEL, CE, TLCK, ENRFOSC TRUTH TABLE (LOW = GND, HIGH = VDD) Pin CE input Type high low XOSEL input high low ENRFOSC input high low TLCK output high low Level Chip enabled Chip disabled Internal Crystal oscillator selected External TCXO connected on REF selected Internal RF oscillator selected External RF oscillator connected on TK1, NTK1 pins Synth. locked Synth. unlocked Result
ADDITIONAL OPTIONAL INTERFACE INFORMATION (REF) Symbol VDC Rin Parameter REF DC voltage Input resistance XOSEL low XOSEL low Test Condition Min. VDD1.1 Typ. VDD0.9 70K Max. VDD0.7 Unit V
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STA001
FUNCTIONAL DESCRIPTION Receiver chain The receiver chain transforms the RF frequency signals to an IF signal at 1.84 MHz Carrier directly usable by the Channel decoder. In front of the STA001 IC it can be placed an external LNA and a bandpass filter; the bandpass filter limitates the input bandwidth and guarantees a suitable rejection to the image frequency. The STA001 input stage is a LNA working in the 1452-1492 MHz band. The RF signal is downconverted, using an active mixer, to a first IF of 115.244 MHz. The first LO is tunable with a frequency step of 460 KHz. The RF can be reduced 5dB by an external trimmer/resistor connected between PADJ1 and PADJ2 pins. An IF variable gain amplifier guarantees 54 dB typical of gain range. Using pins GADJ1, GADJ2, the output RX signal level can be decreased to the desired value by an external trimmer/resistor. Moreover, the IF chain can be configured to have a fixed gain by fixing statically control voltages on AGC1 and AGC2 pins (i.e. V(AGC1)=VCC and V(AGC2)=GND), and by trimming the gain through connecting an external resistor between GADJ1 and GADJ2. By using an 800 Ohm resistor connected between GADJ1 and GADJ2, for example, a typical 56 dBs IF static gain is obtained. The first IF signal, having a bandwidth of 2.5 MHz, shaped by an external SAW filter, is downconverted to a second IF of 1.84 MHz. A differential clock output at 14.72 MHz is available to be used from the baseband. Synthesizers, PLL, charge pump and VCOs The first Voltage controlled Oscillator is controlled by an integrated PLL and it's able to cover a frequency range of 37MHz with a step size of 460 KHz. The second Voltage controlled oscillator produces a fixed 117.08MHz frequency controlled by a second integrated PLL. Moreover, the 2nd PLL is able to select 2 other fixed frequencies, i.e. 111.76MHz and 122.4MHz, suitable for application test. The other components of the first PLL synthesizer are a low frequency programmable divider and a dual modulus prescaler; a fixed dividers is instead used to synthesize the second VCO frequency. Other fixed internal dividers are used to get the comparation frequencies of both loops. Channel selection is made through the I2CBUS interface , directly from the P. POWER SUPPLIES The chip operates from an unregulated power supply of 2.7 to 3.3 Volts. All interface circuits to the baseband chips are operating between these supplies unless otherwise specified. INTERFACE SPECIFICATION All the interface voltage levels to the micro controller are referenced to the supply voltage of the interface power supply (GND) . The interface voltage levels are therefore fully compatible with the base band circuits. The digital levels are all CMOS threshold compatible with the exception of M_CLK1, M_CLK2 pins (ECL type). For completeness all other interface signals are also included. I2C BUS INTERFACE Data transmission from microprocessor to the STA001 takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected to SDA and SCL).
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STA001
Data Validity The data on the SDA line must be stable during the high period of the clock. The HIGH to LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop conditions A start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte format Every byte transferred on the SDA line must contains bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse. The peripheral (STA001) that acknowledges has to pull-down (LOW) the SDA line during the clock pulse. The STA001 which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at at the HIGH level during the ninth clock pulse time. In this case the P can generate the STOP information in order to abort the transfer. Transmission without acknwoledge Avoiding to detect the acknowlegde of the STA001, the P can use a simpler transmission: simply it waits one clock period without checking the STA001 acknowledging, and sends the new data. This approach of course is less protected from misworking. Figure 2. Validity on the I2CBUS
SDA
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
Figure 3. Timing Diagram of the I2CBUS
SCL I2CBUS SDA
D99AU1032
START
STOP
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STA001
Figure 4. Acknowledge on the I2CBUS
SCL
1
2
3
7
8
9
SDA MSB START
D99AU1033
ACKNOWLEDGMENT FROM RECEIVER
TIMING SPECIFICATION Figure 5. Data and clock
SDA SCL
tcwl tcs
Symbol tcs tch tcwh tcwl
tch
tcwh
Minimum time (ns) 100 50 100 100
Parameter Data to clock set up time Data to clock hold time Clock pulse width high Clock pulse width low
Figure 6. Start and stop
SDA SCL
tstart1 tstart2
tstop2tstop1
Symbol Tstart1,2 Tstop1,2
Parameter Clock to data start time Data to clock down stop time
Minimum time (ns) 100 100
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STA001
Figure 7.
SDA SCL 8 9
td2
td1
Symbol td1 td2 Ack begin delay Ack end delay
Parameter
Maximum time (ns) 200 200
SOFTWARE SPECIFICATION Interface protocol The interface protocol comprises: - A start condition (S) - A chip address byte - A two data bytes - A stop condition (P)
MSB chip address LSB MSB 1st data byte LSB MSB 2nd data byte LSB
S
1
1
0
0
0
0
0
0 ack 1 D6 D5 D4 D3 D2 D1 D0 ack 0 D6 D5 D4 D3 D2 D1 D0 ack
P
ack = Acknowledge S = Start P = Stop "Byte by byte" option A "byte by byte" programming mode is also possible when there is no need to use both data bytes to program the chip (for example during the setup of 2nd PLL). To use this feature remember that first bit of both data bytes is reserved to chose the destination of the remaining 7 bits.
MSB chip address LSB MSB 1st data byte LSB
S
1
1
0
0
0
0
0
0
ack
K
D6
D5
D4
D3
D2
D1
D0
ack
P
ack = Acknowledge S = Start
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STA001
P = Stop K= destination of the remaining 7bit: K=1 the data byte has the same function of the 1st data byte in the normal programming mode. K=0 the data byte has the same function of the 2nd data byte in the normal programming mode. Table 1. First data byte selection table (selection of synthesizer channel) using a 14.72Mhz quartz
MSB LSB RF LO freq. selected Units Division ratio selected on synthesizer from REF1 to LO1 1324.8+6*0.46 (1327.56) 1324.8+7*0.46 1324.8 + 8*0.46 MHz MHz MHz 360.75 360.875 361 Lowest selectable freq. Notes
D6 0 0 0 0 -
D5 0 0 0 0 -
D4 0 0 0 1 -
D3 0 0 1 1 -
D2 1 1 0 1 -
D1 1 1 0 0 -
D0 0 1 0 1 1338.14 1324.8 + N*0.46 N=(D6..D0) represented decimal number 1375.4 MHz MHz
363.625 360 + N*0.125
first used freq. general freq. generation rule
1 1 0 0 1
1 1 0 0 0
0 1 0 0 0
1 1 0 0 0
1 1 0 1 1
1 1 0 0 0
0 1 0 1 1
MHz
373.75
Last used freq.
1383.22 1383.68
MHz MHz
375.875 376
1324.8+133*0.46 (1385.98) 1356.54
MHz MHz
376.625 368.625
Highest selectable freq. Startup presetted data
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STA001
Table 2. First data byte selection table (selection of synthesizer channel) using a 14.725Mhz quartz
MSB D6 0 D5 0 D4 0 D3 0 D2 1 D1 1 LSB D0 0 1325.25 +6*0.46015625 (1328.010938) 1325.25 +7*0.46015625 1325.25+ 8*0.46015625 MHz RF LO freq. selected Units Division ratio selected on synthesizer from REF1 to LO1 360.75 Lowest selectable freq. Notes
0 0 0 -
0 0 0 -
0 0 1 -
0 1 1 -
1 0 1 -
1 0 0 -
1 0 0 -
MHz MHz
360.875 361
1338.134375 1325.25+ N*0.46015625 N=(D6..D0) represented decimal number 1375.407031
MHz MHz
363.5 360 + N*0.125
first used freq. general freq. generation rule Last used freq.
1 1 1 0
1 1 1 0
0 1 1 0
1 1 1 0
1 1 1 1
0 1 1 0
1 0 1 1
MHz
373.625
1383.229688 1383.689844
MHz MHz
375.75 375.875
1325.25 +133*0.46015625 (1386.450781) 1357.000781
MHz
376.625
Highest selectable freq. Startup presetted data
1
0
0
0
1
0
1
MHz
368.625
Table 3. Second data byte selection table (LOCK test on both pll, dividers test and IF pll test)
MSB D6 0 0 0 0 0 0 0 1 1 D5 0 0 0 0 0 0 0 0 1 D4 0 0 0 1 1 1 1 0 0 D3 0 0 0 0 1 0 1 0 0 D2 0 1 0 0 0 1 1 0 0 D1 0 0 0 1 1 1 1 0 0 LSB D0 0 0 1 0 0 0 0 0 0 Working mode Lock test on RF pll Lock test on IF pll Lock test on RF and IF pll First pll programmable divider test First pll reference divider test Second pll fixed divider test Second pll reference divider test Test frequency on IF pll divider by 1034 Test frequency on IF pll divider by 1034 Notes lock flag to be tested: TLCK; Startup presetted data lock flag to be tested: TLCK lock flag to be tested: TLCK output freq. divided by 16 available on TLCK output freq. divided by 8 available on TLCK output freq. divided by 2 available on TLCK output freq. available on TLCK Division ratio changed to 987 Division ratio changed to 1081
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2
2
5
6
C10 U1 VN4 SOP SON VN4 AGC1 AGC2 VP4 NTK2 TK2 VP4 FLT2 C11 220nF 44 43 42 41 40 39 38 37 36 35 34
1nF
VP4a
1:4
NEOSID 553210
2 2
2 2 2
2
VP2 TK1 NTK1 VP2 FLT1 VN2 XTAL1 XTAL2 REF XOSEL TLCK
JUMPER2 VP2a L4 1nH VP2b
12 13 14 15 16 17 18 19 20 21 22
+ C37 8pF L5 1nH
C33 100pF
C31 10uF
R17 50
C34 8pF
C35 1nF
C36 100nF
VCC
C39 100pF
VCC
NOTE: Connect a resistor from10K to 100K between pins PADJ1 (9) and PADJ2 (10) so to obtain intermediate gain between 25 and 30dB
C41 100pF
2
16/20
VCC R1 AGC2 T1 680pF R2 D1 D2 VCC C4 AGC1 330pF 100K C6 100nF T2 1 C9 220nF 4 VP4b 1 2 C8 1nF J3 C7 3.3 nF R6 18 k 5.6 K R5 C5 1nF R4 MA372J MA372J C3 100nF 1 4 5 6 2 C2 1nF 100K C1 L1 68nH L2 68nH
STA001
J1
IF2 IN
1
SMA
R3 50
1:1
NEOSID 553200
J2
IF1 OUT
1
SMA
R7 50
RXI OUT
SMA
SMA 1 J4
NRXI OUT
CE R8 R9 1K C15 10nF SCL SDA
VP1 T3 1 STA001 VP3 4 R10 5 LDB20C500A1500 JP1 VCC 1 3 2 4 6 C14 8pF 2 C13 8pF
Figure 8. Test Board Schematic Diagram
J5
C12
RF IN
1
SMA
TEST AND APPLICATION BOARD SCHEMATIC
L3
1:1
1 2 3 4 5 6 7 8 9 10 11 VP1 SIP SIN VN1 LNI NLNI VN1 NC PADJ1 PADJ2 ENRFOSC R11 4.7K R12 4.7K RXI NRXI GADJ1 GADJ2 CE VP3 SCL SDA VN3 M_CLK1 M_CLK2
33 32 31 30 29 28 27 26 25 24 23
VCC
C16 10nF CLK1
VCC C17 8pF R13 1K
C19 100pF
C20 10nF CLK2 T_LOCK JP2 R14 0 R15 390 C23 1 3 C27 Y1 C30 C29 150nF CRYSTAL C28 10nF 1 SMA J6 2 4 VCC
VCC D3 HVU355
C22 100pF
VCC D4 VCC HVU355 R16 1K
C26 100pF
C24 15nF
VCC
R1 AGC VCC 18 17 16 15 15 15 14 14 14 13 12 11 10 10K U1 GND IN IN GND GND GND NC NC GND L1 68nH C1 680pF D1 D2 VCC C2 100nF MA2S372 MA2S372 R2 330pF 5.6 K C4 3.3 nF R3 18 k J1 VP4a 33 C8 VN4 SOP SON SON SON VN4 VN4 VN4 AGC1 AGC1 AGC1 AGC2 VP4 NTK2 TK2 VP4 FLT2 22p U2 2 2 2 44 43 42 41 40 39 38 37 36 35 34 C7 150nF 1 SMA VP4b R4 C3 L2 68nH
S+M Y012B GND NC NC GND GND GND OUT OUT GND 1 2 3 4 4 4 5 5 5 6 7 8 9 100nH VCC L3
C5 100p
C6 10n
RXI O
2 2 2 C9 150nF
VP1 R5 33K 1 STA001 VCC C15 Q1 2.2p L7 2SC5096 5 6 C16 VCC VP2 TK1 NTK1 NTK1 NTK1 VP2 VP2 VP2 FLT1 FLT1 FLT1 VN2 XTAL1 XTAL2 REF XOSEL TLCK 8pF 4 T1 2 C14 8pF L4 56nH
SMA 1 J2
J3 I 100p 1 GND GND GND GND 3 O 4 C12 C13 6.8p
C10
C11
S+M B69813-N1477-A840
NRX
RF IN
1
3
5p
VP3 SCL SDA
SMA
100p
2
L6 7.5nH
1:1
1 2 5 6
2
L5 100nH U3 L8 6.8nH LDB20C500A1500
1 2 3 4 5 6 7 8 9 10 11 VP1 SIP SIN VN1 LNI NLNI VN1 NC PADJ1 PADJ2 ENRFOSC RXI NRXI GADJ1 GADJ2 CE VP3 SCL SDA VN3 M_CLK1 M_CLK2
33 32 31 30 29 28 27 26 25 24 23
Figure 9. Application Board Schematic Diagram
ANT +B VP2a L9 2.2nH VP2b
12 13 14 15 16 17 18 19 20 21 22
Suggested minimum differential RLoad on RXI and NRXI output 3K
R6 4.7K R7 4.7K VCC C20 10nF C19 8pF R8 1K VCC C21 10nF CLK2 D3 HVC355B R9 0 R10 390 C23 T_LOCK CLK1 C26 Y1 C28 C27 150nF CRYSTAL VCC C31 8pF L10 2.2nH C32 1nF D4 HVC355B R11 1K C24 15nF
C17
C18
10n
100p
VCC
C22 100pF
VCC
C25 100pF
VCC
C30 100pF
VCC
C33 100pF
VCC
C34 100pF
STA001
17/20
STA001
Application note: the crystal oscillator must have the following features:
Symbol Parameter Test Condition Min. Typ. Max. Unit
CRYSTAL OSCILLATOR (T = 25, VP-VN = 3V) fxtal1 fxtal2 Pn VDC Quartz frequency Quartz frequency Phase noise XTAL1, XTAL2 common mode DC voltage - Resonance mode: series - Using a 14.72 - Resonance mode: series - using a 14.725 quartz f = 1 KHz XOSEL high VP-1.1 14.72 14.725 -120 VP-0.9 -118 VP-0.7 MHz MHz dBc/Hz V
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STA001
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.30 0.09
mm TYP. MAX. 1.60 0.15 1.40 0.37 1.45 0.45 0.20 12.00 10.00 8.00 0.80 12.00 10.00 8.00 0.60 1.00 0.75 0.018 0.002 0.053 0.012 0.004 MIN.
inch TYP. MAX. 0.063 0.006 0.055 0.014 0.057 0.018 0.008 0.472 0.394 0.315 0.031 0.472 0.394 0.315 0.024 0.039 0.030
OUTLINE AND MECHANICAL DATA
TQFP44 (10 x 10)
0(min.), 3.5(typ.), 7(max.)
D D1 A A2 A1
33 34 23 22
0.10mm .004 Seating Plane
E1
B
44 1 11
12
E
B
C
e
L
K
TQFP4410
19/20
STA001
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
20/20
(R)

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